Summary
Overview
Work History
Education
Skills
Websites
Languages
Timeline
Generic
Vic Chang

Vic Chang

Semiconductor Packaging R&D
Taipei City,30

Summary

A skilled engineering manager builds and motivates high-performing engineering team. Over 10 years of experience in Semiconductor industry working with new product definition, introduction, development and ramp monitoring. Committed to rapidly and efficiently completing projects by leveraging team-based frameworks to best leverage available engineering talent.

Internal papers and publications:

2021 Asia packaging conference - Best paper & Golden Award

2022 Asia packaging conference - Best paper & Golden Award

2022 SCP Impact Award

2024 Technical Leadership Conference - Best paper

Patent disclosure:

22 IP disclosures, 3 approved to file and 5 filed.

Overview

10
10
years of professional experience
2
2
years of post-secondary education

Work History

Packaging Engineering Manager

Texas Instruments
New Taipei City
09.2022 - Current

Power and Sensing platform lead in TI Taiwan.

  • Lead cross-functional teams for successful product development, identify gaps, and ensure timely delivery tied to risk assessment.
  • Managed crisis situations, implementing solutions to address unexpected challenges, to keep project momentum.
  • Provide strategies and define executive plan for BOM/tool multi-source.
  • Cultivate innovation with a clear problem statement, lead brainstorming, and empower the team to provide cutting-edge engineering solutions, setting new industry benchmarks.
  • Enhance overall team productivity with continuous training and mentoring of junior engineers.

Sr. Semiconductor Packaging Engineer

Texas Instruments
New Taipei City
09.2020 - 09.2022

Driving the development and assembly lead for Reinforced Isolation power module, magnetic current sensing products in TI Taiwan.

  • Managed 6 projects simultaneously, prioritizing tasks effectively to meet tight deadlines without compromising quality across different organizations and time zones.
  • Hands-on person to conduct proof-of-concept all the time.
  • Ensured compliance with industry regulations, maintaining up-to-date knowledge on packaging standards and guidelines.
  • Optimized semiconductor package design through exploring new design, BOM, and equipment.
  • Identified opportunities for cost-saving measures in existing processes while maintaining or improving packaging effectiveness and lowering COO.
  • Served as a subject matter expert for packaging-related inquiries and provided training to junior team members on best practices in semiconductor package engineering techniques.

Sr. Process Engineer

ASE Technology Holding Co., Ltd.
09.2014 - 09.2020
  • Well experienced in wafer back grinding, dicing, and flip chip die attach process.
  • NPI evaluation, development, and ramp monitoring.
  • Sustain HVM line, UPH improvement, and drive cost reduction activities.
  • FMEA and Control plan maintenance.
  • Customer voice and 8D report handling.
  • DoE and data analysis via JMP.

Education

Master's Degree of Chemical Engineering -

National Taiwan University of Science And Technology
Taipei City
09.2012 - 05.2014

Skills

DoE and data analysis via JMP

Package Design Rule

Reliability Test

FMEA

SPC

8D Report

Languages

Chinese
Proficient
C2
English
Proficient
C2

Timeline

Packaging Engineering Manager

Texas Instruments
09.2022 - Current

Sr. Semiconductor Packaging Engineer

Texas Instruments
09.2020 - 09.2022

Sr. Process Engineer

ASE Technology Holding Co., Ltd.
09.2014 - 09.2020

Master's Degree of Chemical Engineering -

National Taiwan University of Science And Technology
09.2012 - 05.2014
Vic ChangSemiconductor Packaging R&D