Ron Rudolf De Guia
Yokohama City
Summary
Digital Design Engineer with over 13 years of expertise in RTL design, verification, and backend implementation. Specializes in high-speed, low-power IC design across advanced node processes, including 5nm, 7nm, 12nm, 16nm, and 28nm. Proficient in Cadence Innovus, Synopsys PrimeTime, and various scripting languages to drive innovative solutions.
Overview
16
16
years of professional experience
Work History
Implementation Engineer
ZDRIVE / NSW
2019.02 - Current
- Executed intricate IC designs for various applications, including automotive power sensing and data storage, leveraging advanced TSMC process nodes (5nm, 7nm, 12nm, 28nm).
- Conducted comprehensive static timing analysis (STA) to achieve precise timing closure on high-frequency designs operating at 2.5 GHz.
- Designed and implemented specialized clock design specifications, focusing on optimal cell placement and routing for improved performance.
- Applied custom specifications in clock tree synthesis (CTS) to achieve optimal performance through improved skew and latency.
- Directed static timing analysis (STA) and eco implementation initiatives to enhance design performance.
- Proficiently used Cadence Innovus and Synopsys PrimeTime.
- Projects involved (Customer SocioNext Japan)
- M2V – DLSR Process: TSMC 12nm
- PT200 – Power Sensor Process: TSMC 7nm
- BVA3 – Optical disk drive controller Process - 28nm
- LCR – Printer image processing Process - 28nm
- Horta – SoC for robot taxi Process – TSMC 5nm
- NBSwitch Process – TSMC 5nm
- XP5 – Automotive (e-car) Process – 7nm
- RTCH – High end oscilloscope Process – 16nm
- Collaborated with cross-functional teams to define project requirements and deliverables.
Digital Development Engineer
ROHM LSI Design Philippines Inc.
2010.11 - 2019.01
- Senior Logic Integration Engineer responsible for RTL design, verification, and backend implementation.
- Conducted RTL and Gate-level verification, ensuring design integrity and functionality.
- Performed RTL Synthesis, Fault analysis, IDDQ analysis, and Formality checks.
Education
BS - Computer Engineering
System Technology Institute
Biñan City2010-01
Skills
- Backend Implementation: Cadence Innovus, Synopsys PrimeTime, STA, CTS, ECO, Clock Design, SDC Management
- Frontend Design & Verification: RTL Design, RTL Verification, RTL Synthesis, Gate-Level Verification, Fault Analysis, IDDQ Analysis, Formality Check
- Programming & Scripting: Java, C, VB, Perl, TCL
- Process Nodes: TSMC 5nm, 7nm, 12nm, 16nm, 28nm
- Troubleshooting (Hardware & Software)
- Analytical Problem Solving
- Scripting for Efficiency Enhancement
- Currently studying Python scripting
Timeline
Implementation Engineer
ZDRIVE / NSW
2019.02 - Current
Digital Development Engineer
ROHM LSI Design Philippines Inc.
2010.11 - 2019.01
BS - Computer Engineering
System Technology Institute