Parvathalu Neela
Summary
Principal DV Engineer with 19+ years of experience in IP/SOC integration, front-end verification, and leadership across domains including PCIe, Ethernet, WLAN, and AI accelerators. Proven expertise in SystemVerilog/UVM methodologies, delivering complex verification projects with high quality and efficiency.
Overview
20
20
years of professional experience
Work History
Principal Engineer
Marvell
Bangalore
12.2022 - Current
- Leading PCIe Gen6 MAC + Serdes verification (PEMC subsystem).
- Integrated PCIe MAC with COMPHY Serdes; executed compliance test suites with Avery PCIe VIP.
- Verified Gen6 features including flit mode, L0p, link training, and auto-negotiation.
- Developed test suites for Ethernet features in COMPHY Serdes (112G/224G).
- Mentored 3–4 junior engineers, ensuring regression stability and coverage closure.
SMTS
AMD
Hyderabad
01.2019 - 12.2022
- Directed SOC-level integration and verification of GFX IP and IPU (AI accelerator).
- Achieved 100% regression stability, toggle coverage, and DVLEC checks across multiple projects.
- Managed teams of up to 5 engineers, coordinating cross-functional efforts across geographies.
- Delivered multiple SOC deployments for gaming consoles, desktops, and notebooks.
Sr Design Engineer II
Xilinx
Hyderabad
08.2017 - 12.2018
- Maintained regression stability for Ethernet IP cores supporting 10Mbps–200Gbps speeds.
- Focused on debugging and stabilizing 10G/20G/40G Ethernet IP regressions.
Sr R&D Engineer I
Synopsys
Hyderabad
09.2011 - 08.2017
- Developed SV UVM testbench components, random stimulus, and functional coverage.
- PCIe VIP: Implemented PHY layer test suites for LTSSM and link training (Gen3/Gen4).
- Ethernet VIP: Verified MAC/PHY layers, auto-negotiation (Clause 73), and link training (Clause 72/92/136/162).
- Delivered customer support and regression automation.
Verification Engineer
nSys Design Systems
New Delhi
08.2010 - 09.2011
- Verified Ethernet EEE features using OVM methodology.
- Developed functional coverage and test sequences for low-power idle mode.
Asst. Engineer
Silicon Interfaces
Mumbai
08.2006 - 07.2010
- Designed and verified WLAN MAC with PCIX bus interface (IEEE 802.11 a/b/g).
- Verified Ethernet MAC with DMA controller (10/100 Mbps).
- Developed RTL modules for WLAN MAC header assembly and synchronizers.
Education
M.Tech - VLSI System Design
Jawaharlal Nehru Technical University
Hyderabad01-2006
Skills
- SystemVerilog
- Verilog, VHDL
- UVM, OVM, VMM
- PCIe (Gen3/Gen6 PHY)
- Ethernet (MAC/PHY)
- WLAN(MAC)
- AI accelerators
- Error orrecting Coder(Viterbi soft out put))
- VCS, Verdi, QuestaSim, NC-Sim, DVE
- Windows, Linux
- IP/SOC integration, Verification
- Serdes bring-up
- CSR register verification
- Regression automation
Accomplishments
- Successfully delivered PCIe Gen6 subsystem verification ahead of schedule.
- Achieved 100% regression stability across multiple SOC deployments at AMD.
- Introduced automation frameworks that reduced regression cycle time by 30%.
- Mentored junior engineers who later transitioned into lead roles.
- Recognized for cross-functional collaboration across geographies.
Custom
- Led verification teams of up to 5 engineers across AMD and Marvell projects.
- Delivered multiple SOC deployments with 100% regression stability and coverage closure.
- Automated regression flows using Jenkins for continuous integration.
- Strong experience collaborating with cross-functional teams across geographies.
Timeline
Principal Engineer
Marvell
12.2022 - Current
SMTS
AMD
01.2019 - 12.2022
Sr Design Engineer II
Xilinx
08.2017 - 12.2018
Sr R&D Engineer I
Synopsys
09.2011 - 08.2017
Verification Engineer
nSys Design Systems
08.2010 - 09.2011
Asst. Engineer
Silicon Interfaces
08.2006 - 07.2010
M.Tech - VLSI System Design
Jawaharlal Nehru Technical University