Summary
Overview
Work History
Education
Skills
Publications
Timeline
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Nadia Farheen

Nadia Farheen

Design Verification Engineer
Tokyo

Summary

Results-driven ASIC Verification Engineer with over three years of semiconductor industry experience, specializing in UVM and SystemVerilog. Proven to drive significant advancements in coverage closure and verification efficiency by expertly analyzing and resolving complex digital design challenges. Passionate about high-performance computing verification, including CPU architectures and SoC blocks, eager to deliver cutting-edge silicon solutions

Overview

4
4
years of professional experience
3
3
Languages

Work History

Verification Engineer

Ampere Computing
11.2021 - Current
  • Architectured and implemented robust UVM-based test environments aligned with detailed design specifications.
  • Developed and deployed reusable UVM components (tests, sequences, agents, interfaces, monitors, assertions, checkers, cover-bins), enhancing verification efficiency by 25%.
  • Owned end-to-end functional verification of critical CPU and SoC blocks, including Current Limit Manager (CLM), Instruction per second Data Collector (IDC), and ARM Generic Interrupt Controller (GIC), ensuring functional correctness.
  • Achieved >95% toggle and functional coverage closure on complex ASIC designs, reducing verification cycles.
  • Developed C test cases to support comprehensive CPU validation efforts, strengthening CPU functionality and performance.
  • Proactively deployed SystemVerilog Assertions (SVAs) for power management blocks, enhancing design reliability and identifying pre-silicon issues.
  • Designed and implemented robust checkers for power management and clock controllers, ensuring system stability.
  • Conducted thorough reviews of customer documentation, providing actionable feedback that drove product enhancements.
  • Systematically documented, triaged, and resolved numerous software defects, collaborating with development teams for timely resolutions.

Engineering Intern

Mentor Graphics
10.2019 - 05.2020
  • Executed comprehensive UVM-based functional verification of the SPI protocol in QuestaSim.
  • Implemented SVA-based verification for the APB 3.0 Protocol, deploying comprehensive SystemVerilog assertions.
  • Migrated a legacy SystemVerilog testbench for a synchronous FIFO to a modern UVM-based environment, significantly enhancing testbench reusability and efficiency.
  • Engineered DDR3 schematics and layouts (PADS Pro) and performed signal integrity analysis (HyperLynx) to verify design integrity.

Summer Intern

Mentor Graphics
06.2019 - 07.2019
  • Applied SystemVerilog (SV) testbench methodologies for functional verification of complex digital designs.
  • Utilized Mentor Graphics QuestaSim for efficient RTL simulation and debugging.
  • Validated the functionality of a Universal Memory Controller, ensuring robust performance and specification adherence.
  • Implemented and verified a synchronous FIFO, guaranteeing data integrity and timing accuracy.
  • Validated data and control paths of an LC3 microcontroller, confirming specification adherence.

Education

M. Tech - VLSI Design

Amrita School of Engineering
01.2020

Skills

Verification Methodologies: UVM, SystemVerilog, Assertion-Based Verification (SVA), Coverage-Driven Verification (CDV), Functional Coverage Closure, Code Coverage, Testbench Architecture, Post-Silicon Validation Concepts

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Publications

Farheen, N., & Pande, K. S. (2020). Error Detection and Correction Using RP SEC-DED. 4th IEMENTech 2020 IEEE Conference, IEM, Kolkata, India.

Timeline

Verification Engineer

Ampere Computing
11.2021 - Current

Engineering Intern

Mentor Graphics
10.2019 - 05.2020

Summer Intern

Mentor Graphics
06.2019 - 07.2019

M. Tech - VLSI Design

Amrita School of Engineering

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Nadia FarheenDesign Verification Engineer