Summary
Overview
Work History
Education
Skills
Websites
Personal Information
Publications
Internships Workshops
Timeline
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Nadia Farheen

Summary

Highly motivated and results-driven ASIC Verification Engineer with over three years of experience in the semiconductor industry, specializing in UVM and SystemVerilog. Proven track record of delivering significant improvements in coverage closure and verification efficiency. Expertly analyzes and resolves complex digital design challenges through collaborative efforts with cross-functional teams. Passionate about high-performance computing verification, including CPU architectures, and eager to contribute to the development of cutting-edge silicon solutions.

Overview

3
3
years of professional experience

Work History

Verification Engineer

Ampere Computing
Bangalore
11.2021 - Current
  • Verification Engineer, Ampere Computing, Bangalore
    Architected comprehensive verification strategies by translating complex project
    requirements, ensuring robust alignment with detailed design specifications.
    ●
    Developed and implemented reusable UVM components, including tests, sequences,
    agents, interfaces, binds, monitors, assertions, checkers, and cover-bins, significantly
    enhancing verification efficiency and testbench reusability.
    ●
    Owned the comprehensive verification of key CPU and SoC blocks, including the Current
    Limit Manager (CLM), Instruction per second Data Collector (IDC), and ARM Generic
    Interrupt Controller (GIC), ensuring their functional correctness and performance
    ●
    Achieved substantial improvements in toggle and functional coverage closure, ensuring
    exhaustive design verification for complex ASIC designs.
    ●
    Developed C test cases to support comprehensive CPU validation efforts, strengthening
    CPU functionality and performance.
    ●
    Proactively investigated and deployed assertions for power management blocks
    throughout the project lifecycle, enhancing design reliability and stability.
    ●
    Designed and implemented checkers for power management and clock controllers,ensuring overall system stability and reliability.
    Conducted thorough reviews of customer documentation, providing actionable feedback
    to drive product enhancements, and improve verification quality.
    ●
    Systematically documented, triaged, and resolved software defects, collaborating
    effectively with development teams to ensure timely resolutions.

Engineering Intern

Mentor Graphics
Bangalore
10.2019 - 05.2020
  • Executed functional verification of the SPI protocol, utilizing a UVM testbench
    within the Mentor Graphics QuestaSim environment.
    ●
    Implemented robust SVA-based verification for the APB 3.0 Protocol, designing and
    deploying comprehensive SystemVerilog assertions.
    ●
    Migrated a legacy SystemVerilog testbench for a synchronous FIFO to a modern
    UVM-based verification environment, significantly enhancing testbench reusability and
    efficiency.
    ●
    Engineered DDR3 schematics and layouts using PADS Pro, performing thorough signal
    integrity analysis with HyperLynx to ensure optimal performance

Summer Intern

Mentor Graphics
Bangalore
06.2019 - 07.2019
  • Applied expertise in functional verification methodologies using SystemVerilog (SV)
    testbench environments for complex digital designs.
    ●
    Utilized Mentor Graphics QuestaSim for efficient RTL simulation and debugging. ●
    Validated the functionality of a Universal Memory Controller, ensuring robust
    performance.
    ●
    Implemented and verified a synchronous FIFO, guaranteeing data integrity and timing
    accuracy.
    ●
    Confirmed adherence to specifications by validating the data and control paths of an
    LC3 microcontroller

Education

M. Tech - VLSI Design

Amrita School of Engineering
Bangalore, India
06.2018 - 04.2020

B. Tech - Electronics and Communication

GSSSIETW
Mysore, India
01.2018

Skills

  • Verification methodologies: UVM (Universal Verification Methodology), SystemVerilog, assertion-based verification (SVA), coverage-driven verification (CDV), functional coverage, code coverage, testbench architecture
  • Hardware description languages (HDLs): Verilog, SystemVerilog, and UVM
  • Protocols and interfaces: AXI, AHB, APB, SPI, I2C, DDR3
  • EDA tools: Mentor Graphics QuestaSim, Synopsys VCS, ModelSim, Synopsys Verdi, Cadence Genus, Mentor Graphics HyperLynx, LTspice, and Xilinx Vivado, PADS Pro
  • Design concepts: digital design, ASIC design flow, computer architecture, CPU verification, SoC verification, power management, clock controllers, memory controllers, FIFOs
  • Programming: C/C (for test cases), Tcl (familiarity)

Personal Information

Visa Status: HSP dependent Japan Visa

Publications

Error Detection and Correction Using RP SEC-DED, Nadia Farheen, Kirti S. Pande, 4th IEMENTech-2020 IEEE Conference, IEM, Kolkata, India

Internships Workshops

  • Online Course on VLSI covering Analog and Digital ASIC design Flow, NIELIT Calicut, 01/15/18, 01/26/18
  • Short Term Training Program on Emerging Trends in VLSI Design, SVNIT Gujarat, 12/25/17, 12/29/17
  • Training program on IP networking of broadband services, RTTCBSNL, Mysore, 12/18/17, 12/22/17
  • Secured First Prize in Inter-college Circuit Debugging Competition, GSSS Mysore, 12/18/17, 12/22/17

Timeline

Verification Engineer

Ampere Computing
11.2021 - Current

Engineering Intern

Mentor Graphics
10.2019 - 05.2020

Summer Intern

Mentor Graphics
06.2019 - 07.2019

M. Tech - VLSI Design

Amrita School of Engineering
06.2018 - 04.2020

B. Tech - Electronics and Communication

GSSSIETW

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