MD. SAIFUL ISLAM
ASIC Design And Verification Engineer
Fukuoka
Summary
Seeking to take up new challenges and gain new experiences as an Electrical & Electronic Engineer to meet my competencies, capabilities, skills, education, and experience.
Overview
8
8
years of professional experience
3
3
Languages
Work History
RTL Coding and Verification Engineer
Sony semiconductor by HCL Japan
3 2021
- Demonstrated understanding of design specifications, data flow, and timing charts
- Developed RTL for various modules including SRAM controller and color filter, ensuring linting
- Implemented reference module creation using C programming and Python
- Generated test cases and enhanced simulation environment using UVM methodology
- Formulated assertions and functional coverage to ensure accurate verification
- Assessed functional and code coverage reports to identify holes and potential improvement
- Conducted thorough analysis of simulation results, addressing any discrepancies with detailed explanations
- Reviewed waveforms and produced comprehensive simulation result reports
PnR Floor planning to CTS (Low power design)
Toshiba Information Technology by BJIT
2020.11 - 2021.02
- Floor planning
- Check netlist, SDC
- Check macros overlapping make sure no overlapping
- Check PG connection
- Placement
- Check all errors and warnings
- Placement density and Routing congestion
- Check max_cap and max_tran violation and hold time violation
- Clock tree synthesis
- Create TCL script for CTS
- Apply NDR and insert buffer where needed
- Check skew, latency and create skew group
- Check setup and hold time, max_cap and max_trns violation.
Low power verification and placement and creating clock diagram
Toshiba Information Technology by BJIT (Image sensor)
2020.02 - 2020.10
- Write upf of different power domain (Isolation cell insertion, level shifter, power switch)
- Generate power report in PTPX
- Check leakage power and static power
- Compare power report with previous generation report
- If there any power increase in any module find out possible reason and feedback to design team
- Check switching activities (SAIF)
- Physical Design
- Worked from post Synthesis netlist to GDSII
- Functional Netlist check and fix (SpyGlass)
- Script preparation in TCL, PERL for automation
- Static Timing Analysis in PrimeTime.
Synthesis and PnR
Toshiba Information Technology by BJIT
2019.10 - 2020.01
- Worked from post Synthesis netlist to GDSII
- Functional Netlist check and fix (SpyGlass)
- Automation script preparation in TCL, PERL
- Working on block level as an assistant with block owner
- Timing and physical signoff
- Netlist Debug
- SDC Debug
- Write perl script for timing report analysis.
AXI bus verification, Synthesis and PnR
Toshiba Information Technology by BJIT
2019.02 - 2019.09
- AXI bus verification (zebu Synopsys)
- Understand cpu and slave device specification
- Write test case in systemC
- Write assertion and coverage.
Synthesis, Formal Verification and DFT
Toshiba Information Technology by BJIT
2017.12 - 2018.11
- Synthesis (DC tool)
- Set RTL (Verilog and VHDL) and Library
- Writing script for checking error, warning and lint
- Develop synthesis flow in DC tool
- Checklist: Un expandable clock
- If there any registers without clock (check_clock)
- Undriven outputs
- Do not use cells
- IO delay missing
- Multi driven inputs
- Pin direction mismatch
- Clock gating check (normal cell in clock path)
- Formal verification (Formality)
- Develop formal verification flow in Formality
- Set reference and implementation design and library
- Write constraint file
- Check log and debug if there any mismatch
- DFT Insertion (Design compiler)
- DFT flow development in DC
- Check if there any cell violation or broken scan chain
- Coverage report check
- Log check.
Synthesis, Formal Verification and STA
Toshiba Information Technology by BJIT (Image processor)
2016.08 - 2017.09
- STA (PrimeTime/PX)
- Check timing and unconstraint endpoints
- Clock skew check
- Check constraint and global slack reports
- Write script for checking log and timing reports
- Did ECO when a violation occurs in any scenario
- Switching activities and power report check
- Synthesis (DC tool)
- Set RTL (Verilog and VHDL) and Library
- Writing script for checking error, warning, and lint
- Develop synthesis flow in DC tool
- Checklist: Un expandable clock
- If there any registers without clock (check_clock)
- Unconstraint IO
- Floating pin
- Multi driven inputs
- Pin direction mismatch
- Clock gating check (normal cell in clock path).
Education
B.Sc in Electrical & Electronic Engineering (EEE) -
United International University (UIU)
Higher Secondary Certificate in Science Group - undefined
Savar Model College
Secondary School Certificate in Science Group - undefined
Baidgaon High School
Skills
RTL design understanding and coding
Assertion and UVM based verification
SystemVerilog expertise
Code coverage analysis
Verification planning
Testbench development
Scripting languages proficiency
ASIC and FPGA design flow
Constraint Random Verification
Functional Coverage
Timing Analysis
Gate-level simulations
Math Skills
Programing language Skills
Verilog, System Verilog, Perl, Python, TCL, C
Thesis Project
Amplifier and Adder circuit implementation using bilayer Graphene FET
Thesis Project Supervisor
Dr. Iqbal Bahar Chowdhury, Associate Professor, EEE, UIU
Thesis Project Details
Used VerilogA to model and implement the circuit using Virtuoso
Scholarship Achievements
- Semester based scholarship
- 3rd place in undergraduate thesis poster presentation
Field Of Interest
- SoC design
- RTL Coding & Verification
- RTL Synthesis
- STA
- Physical design
- Physical verification
- Formal Verification
- Design for testing (DFT)
Timeline
PnR Floor planning to CTS (Low power design)
Toshiba Information Technology by BJIT
2020.11 - 2021.02
Low power verification and placement and creating clock diagram
Toshiba Information Technology by BJIT (Image sensor)
2020.02 - 2020.10
Synthesis and PnR
Toshiba Information Technology by BJIT
2019.10 - 2020.01
AXI bus verification, Synthesis and PnR
Toshiba Information Technology by BJIT
2019.02 - 2019.09
Synthesis, Formal Verification and DFT
Toshiba Information Technology by BJIT
2017.12 - 2018.11
Synthesis, Formal Verification and STA
Toshiba Information Technology by BJIT (Image processor)
2016.08 - 2017.09
RTL Coding and Verification Engineer
Sony semiconductor by HCL Japan
3 2021
B.Sc in Electrical & Electronic Engineering (EEE) -
United International University (UIU)
Higher Secondary Certificate in Science Group - undefined
Savar Model College
Secondary School Certificate in Science Group - undefined
Baidgaon High School