Masa Higashitani

• Company Overview: (May/2016, Western Digital acquired SanDisk) (2001 ~ May/2016: SanDisk, 2016~ Current: Western Digital)
• Lead overall 3D- NAND Development
• Make technical judgments (New Idea: Wafer-Bonding technology, On-Pitch SGD formation, New operation scheme, etc.)
• Define Chip architecture
• I/O scheme, Power usage, Cell reliability (Coordinate these items with Business Unit)
• Technology transfer work for ~300Layer 3D-NAND
• Coordinate Business Unit requirement and technical challenges (I/O, Cell reliability, Cell performance)
• Establish technology transfer team as scheme for Technology Ramp

Same as above. (SanDisk was spun off as a separate public company from Western Digital)

• 3D-NAND Development (128Layers, 160layers and ~218layers)
• Drive CBA technology for 218Layers 3D-NAND, Lead 128Layer Development
• Define QLC chip architecture
• Cell operation (Read scheme), Cell Reliability, I/O scheme
• Drive QLC device - Bring new process method for 3D NAND cell

• 3D-NAND 96Layers Development & Transfer to Mass Production (Overcome Memory Hole process challenge)
• 3D-NAND 64Layers Development & Transfer to Mass Production (Establish 3D-NAND Mass production)
• Drive 3D-NAND reliability evaluation -
• 1Znm NAND development (Z is number from 0 to 9 and beyond) & Transfer Mass production (Manage Business requirement)
• 1Ynm NAND development (Y is number from 0 to 9 and beyond) & Transfer Mass Production (Introduce STI Air-Gap technology)
• Manage NAND cell design from device operations (Program, Erase, Read, Verify)
• Manage PDK and coordinate with Design/Package
• 19nm/24nm/32nm/ 43nm (1st 4 bits/cell NAND chip in the world) /55nm/70nm/90nm/0.13um/0.16um 2D NAND development
• Making TEST CHIP, -PDK/CMOS/Transistor Model
• Process flow, Device operation (MLC function)

• Company Overview: (Worked at AMD Sunnyvale during 1997~2001)
• 0.18um/0.25um/0.35 NAND Flash memory project manager (Assignee at AMD)
• Created Process flow, EDR and GDR
• Designed test chip, running test chip silicon
• Transferred 0.25um NAND flash memory technology to manufacturing FAB (FASL: Fujitsu AMD Semiconductor Limited) for mass production
• Established baseline D/S flow and Repair scheme
• (Worked at AMD Sunnyvale during 1997~2001)

• 0.35um/0.50um NOR flash project sub leader
• Established 8-inch wafer flash memory process development (Establish Isolation process, Well formation, Self-Align-Source, etc.)
• Transferred 0.35/0.50um NOR flash technologies to FASL for mass production Characterized NOR flash memory product and device reliability
• Working on Analogy Memory architecture with NOR Array Test Chip

• 0.35um DRAM project sub leader
• Test Chip making/Transistor modeling/Engage Phase-shift-Mask technology for DRAM Contributed EDR, GDR and Process flow